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-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:50:33 11/25/2012 
-- Design Name: 
-- Module Name:    addkey - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity addkey is
port ( clk : in std_logic;
		 datain : in std_logic_vector(127 downto 0);
		 subkey : in std_logic_vector(127 downto 0);
		 dataout : out std_logic_vector(127 downto 0)
);
end addkey;

architecture Behavioral of addkey is
begin

process (clk)
begin

	if (rising_edge(clk)) then
		dataout <= datain xor subkey;
	end if;

end process;

end Behavioral;

